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Searched refs:SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7854 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L macro
Dgfx_7_2_sh_mask.h8319 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
Dgfx_8_0_sh_mask.h9573 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
Dgfx_8_1_sh_mask.h9971 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h15571 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
Dgc_9_1_sh_mask.h16880 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
Dgc_9_2_1_sh_mask.h16755 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
Dgc_10_3_0_sh_mask.h21111 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro
Dgc_10_1_0_sh_mask.h22953 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK … macro