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Searched refs:SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h13559 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 macro
Dgfx_8_1_sh_mask.h13957 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2183 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK … macro
Dgc_9_1_sh_mask.h2031 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK … macro
Dgc_9_2_1_sh_mask.h2054 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK … macro
Dgc_10_3_0_sh_mask.h8062 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK … macro
Dgc_10_1_0_sh_mask.h7735 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK … macro