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Searched refs:SQ_EDC_SEC_CNT__VGPR_SEC_MASK (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h298 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK … macro
Dgc_9_0_sh_mask.h3211 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK … macro
Dgc_9_1_sh_mask.h3059 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK … macro
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h14071 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 macro
Dgfx_8_1_sh_mask.h14469 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 macro