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Searched refs:SQ_IND_INDEX__SIMD_ID__SHIFT (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2986 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2998 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
Dgfx_v7_0.c4153 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4165 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
Dgfx_v8_0.c5232 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5244 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
Dgfx_v9_0.c2017 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2029 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h9011 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 macro
Dgfx_7_2_sh_mask.h12402 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
Dgfx_8_0_sh_mask.h14272 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
Dgfx_8_1_sh_mask.h14670 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2621 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro
Dgc_9_1_sh_mask.h2469 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro
Dgc_9_2_1_sh_mask.h2427 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro