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Searched refs:SQ_MTBUF_0__IDXEN_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h9112 #define SQ_MTBUF_0__IDXEN_MASK 0x00002000L macro
Dgfx_7_2_sh_mask.h13037 #define SQ_MTBUF_0__IDXEN_MASK 0x2000 macro
Dgfx_8_0_sh_mask.h14945 #define SQ_MTBUF_0__IDXEN_MASK 0x2000 macro
Dgfx_8_1_sh_mask.h15343 #define SQ_MTBUF_0__IDXEN_MASK 0x2000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2804 #define SQ_MTBUF_0__IDXEN_MASK … macro
Dgc_9_1_sh_mask.h2652 #define SQ_MTBUF_0__IDXEN_MASK … macro
Dgc_9_2_1_sh_mask.h2610 #define SQ_MTBUF_0__IDXEN_MASK … macro