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Searched refs:SQ_WAVE_TTMP5__DATA_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h10036 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL macro
Dgfx_7_2_sh_mask.h12613 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff macro
Dgfx_8_0_sh_mask.h14499 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff macro
Dgfx_8_1_sh_mask.h14897 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h28597 #define SQ_WAVE_TTMP5__DATA_MASK … macro
Dgc_9_1_sh_mask.h29811 #define SQ_WAVE_TTMP5__DATA_MASK … macro
Dgc_9_2_1_sh_mask.h30139 #define SQ_WAVE_TTMP5__DATA_MASK … macro
Dgc_10_3_0_sh_mask.h46620 #define SQ_WAVE_TTMP5__DATA_MASK … macro
Dgc_10_1_0_sh_mask.h42838 #define SQ_WAVE_TTMP5__DATA_MASK … macro