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Searched refs:SR (Results 1 – 25 of 73) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
100 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
101 SR(DCFEV_CLOCK_CONTROL), \
110 SR(BLNDV_CONTROL),\
151 SR(DCHUB_FB_LOCATION),\
152 SR(DCHUB_AGP_BASE),\
153 SR(DCHUB_AGP_BOT),\
154 SR(DCHUB_AGP_TOP)
166 SR(REFCLK_CNTL), \
167 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
[all …]
Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
[all …]
Ddce_abm.h33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
[all …]
Ddce_panel_cntl.h39 SR(BL_PWM_CNTL), \
40 SR(BL_PWM_CNTL2), \
41 SR(BL_PWM_PERIOD_CNTL), \
42 SR(BL_PWM_GRP1_REG_LOCK), \
43 SR(BIOS_SCRATCH_2)
53 SR(BL_PWM_CNTL), \
54 SR(BL_PWM_CNTL2), \
55 SR(BL_PWM_PERIOD_CNTL), \
56 SR(BL_PWM_GRP1_REG_LOCK), \
Ddce_link_encoder.h48 SR(DMCU_RAM_ACCESS_CTRL), \
49 SR(DMCU_IRAM_RD_CTRL), \
50 SR(DMCU_IRAM_RD_DATA), \
51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
77 SR(DCI_MEM_PWR_STATUS)
82 SR(DMCU_RAM_ACCESS_CTRL), \
83 SR(DMCU_IRAM_RD_CTRL), \
84 SR(DMCU_IRAM_RD_DATA), \
85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
115 SR(DCI_MEM_PWR_STATUS)
[all …]
Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
Ddce_i2c_hw.h88 SR(DC_I2C_ARBITRATION),\
89 SR(DC_I2C_CONTROL),\
90 SR(DC_I2C_SW_STATUS),\
91 SR(DC_I2C_TRANSACTION0),\
92 SR(DC_I2C_TRANSACTION1),\
93 SR(DC_I2C_TRANSACTION2),\
94 SR(DC_I2C_TRANSACTION3),\
95 SR(DC_I2C_DATA),\
96 SR(MICROSECOND_TIME_BASE_DIV)
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb.h46 SR(DWB_ENABLE_CLK_CTRL),\
47 SR(DWB_MEM_PWR_CTRL),\
48 SR(FC_MODE_CTRL),\
49 SR(FC_FLOW_CTRL),\
50 SR(FC_WINDOW_START),\
51 SR(FC_WINDOW_SIZE),\
52 SR(FC_SOURCE_SIZE),\
53 SR(DWB_UPDATE_CTRL),\
54 SR(DWB_CRC_CTRL),\
55 SR(DWB_CRC_MASK_R_G),\
[all …]
Ddcn30_hubbub.h40 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
41 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
42 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
43 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
44 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
45 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
46 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
47 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
48 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
49 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
[all …]
Ddcn30_dccg.h34 SR(PHYASYMCLK_CLOCK_CNTL),\
35 SR(PHYBSYMCLK_CLOCK_CNTL),\
36 SR(PHYCSYMCLK_CLOCK_CNTL)
41 SR(PHYASYMCLK_CLOCK_CNTL),\
42 SR(PHYBSYMCLK_CLOCK_CNTL),\
43 SR(PHYCSYMCLK_CLOCK_CNTL)
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.h36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
45 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.h34 SR(DCHUBBUB_CRC_CTRL), \
35 SR(DCN_VM_FB_LOCATION_BASE),\
36 SR(DCN_VM_FB_LOCATION_TOP),\
37 SR(DCN_VM_FB_OFFSET),\
38 SR(DCN_VM_AGP_BOT),\
39 SR(DCN_VM_AGP_TOP),\
40 SR(DCN_VM_AGP_BASE)
47 SR(DCHUBBUB_CRC_CTRL), \
48 SR(DCN_VM_FB_LOCATION_BASE),\
49 SR(DCN_VM_FB_LOCATION_TOP),\
[all …]
Ddcn20_dccg.h32 SR(DPPCLK_DTO_CTRL),\
37 SR(REFCLK_CNTL)
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.h31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
36 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
39 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
40 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
[all …]
/drivers/macintosh/
Dvia-cuda.c47 #define SR (10*RS) /* Shift register */ macro
346 (void)in_8(&via[SR]); in sync_egret()
361 (void)in_8(&via[SR]); in sync_egret()
389 (void)in_8(&via[SR]); /* clear any left-over data */ in cuda_init_via()
398 (void)in_8(&via[SR]); in cuda_init_via()
409 (void)in_8(&via[SR]); in cuda_init_via()
418 (void)in_8(&via[SR]); in cuda_init_via()
546 out_8(&via[SR], current_req->data[data_index++]); in cuda_start()
599 (void)in_8(&via[SR]); in cuda_interrupt()
609 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]
Dvia-macii.c53 #define SR (10*RS) /* Shift register */ macro
180 x = via[SR]; in macii_init_via()
343 via[SR] = req->data[1]; in macii_start()
402 x = via[SR]; in macii_interrupt()
452 x = via[SR]; in macii_interrupt()
465 x = via[SR]; in macii_interrupt()
475 x = via[SR]; in macii_interrupt()
491 via[SR] = req->data[data_index++]; in macii_interrupt()
504 x = via[SR]; in macii_interrupt()
559 x = via[SR]; in macii_interrupt()
/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c282 #define SR(reg) \ macro
293 SR(IRQENABLE); in dispc_save_context()
294 SR(CONTROL); in dispc_save_context()
295 SR(CONFIG); in dispc_save_context()
296 SR(LINE_NUMBER); in dispc_save_context()
299 SR(GLOBAL_ALPHA); in dispc_save_context()
301 SR(CONTROL2); in dispc_save_context()
302 SR(CONFIG2); in dispc_save_context()
305 SR(CONTROL3); in dispc_save_context()
306 SR(CONFIG3); in dispc_save_context()
[all …]
Ddss.c123 #define SR(reg) \ macro
132 SR(CONTROL); in dss_save_context()
136 SR(SDI_CONTROL); in dss_save_context()
137 SR(PLL_CONTROL); in dss_save_context()
163 #undef SR
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr_internal.h94 SR(DENTIST_DISPCLK_CNTL)
98 SR(DENTIST_DISPCLK_CNTL)
106 SR(DENTIST_DISPCLK_CNTL), \
113 SR(DENTIST_DISPCLK_CNTL)
/drivers/gpu/drm/omapdrm/dss/
Ddispc.c415 #define SR(dispc, reg) \ macro
426 SR(dispc, IRQENABLE); in dispc_save_context()
427 SR(dispc, CONTROL); in dispc_save_context()
428 SR(dispc, CONFIG); in dispc_save_context()
429 SR(dispc, LINE_NUMBER); in dispc_save_context()
432 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
434 SR(dispc, CONTROL2); in dispc_save_context()
435 SR(dispc, CONFIG2); in dispc_save_context()
438 SR(dispc, CONTROL3); in dispc_save_context()
439 SR(dispc, CONFIG3); in dispc_save_context()
[all …]
/drivers/media/pci/ngene/
Dngene-core.c79 while (Cur->ngeneBuffer.SR.Flags & 0x80) { in demux_tasklet()
82 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
88 Cur->ngeneBuffer.SR. in demux_tasklet()
102 Cur->ngeneBuffer.SR.Flags &= in demux_tasklet()
115 Cur->ngeneBuffer.SR.Flags &= ~0x40; in demux_tasklet()
122 Cur->ngeneBuffer.SR.DTOUpdate = in demux_tasklet()
131 if (Cur->ngeneBuffer.SR.Flags & 0x01) in demux_tasklet()
133 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
139 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
144 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
[all …]
/drivers/staging/unisys/Documentation/ABI/
Dsysfs-platform-visorchipset59 responsible for enabling and disabling SR-IOV devices when the
62 Some SR-IOV devices have problems when the PF is reset without
78 responsible for enabling and disabling SR-IOV devices when the
81 Some SR-IOV devices have problems when the PF is reset without
/drivers/spi/
Dspi-atmel.c592 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { in atmel_spi_next_xfer_single()
643 (void)spi_readl(as, SR); in atmel_spi_next_xfer_fifo()
1067 status = spi_readl(as, SR); in atmel_spi_pio_interrupt()
1088 spi_readl(as, SR); in atmel_spi_pio_interrupt()
1124 status = spi_readl(as, SR); in atmel_spi_pdc_interrupt()
1135 spi_readl(as, SR); in atmel_spi_pdc_interrupt()
1381 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) in atmel_spi_one_transfer()
1386 while (spi_readl(as, SR) & SPI_BIT(RDRF)) in atmel_spi_one_transfer()
1390 spi_readl(as, SR); in atmel_spi_one_transfer()
1644 spi_readl(as, SR); in atmel_spi_remove()
/drivers/video/fbdev/via/
Dviamode.h15 unsigned char SR[StdSR]; member
/drivers/net/ethernet/qlogic/
DKconfig38 bool "QLOGIC QLCNIC 83XX family SR-IOV Support"
90 bool "QLogic QED 25/40/100Gb SR-IOV support"

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