1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/platform_device.h>
14 #include <linux/spi/spi.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/scatterlist.h>
17
18 #define DRIVER_NAME "rockchip-spi"
19
20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
23 writel_relaxed(readl_relaxed(reg) | (bits), reg)
24
25 /* SPI register offsets */
26 #define ROCKCHIP_SPI_CTRLR0 0x0000
27 #define ROCKCHIP_SPI_CTRLR1 0x0004
28 #define ROCKCHIP_SPI_SSIENR 0x0008
29 #define ROCKCHIP_SPI_SER 0x000c
30 #define ROCKCHIP_SPI_BAUDR 0x0010
31 #define ROCKCHIP_SPI_TXFTLR 0x0014
32 #define ROCKCHIP_SPI_RXFTLR 0x0018
33 #define ROCKCHIP_SPI_TXFLR 0x001c
34 #define ROCKCHIP_SPI_RXFLR 0x0020
35 #define ROCKCHIP_SPI_SR 0x0024
36 #define ROCKCHIP_SPI_IPR 0x0028
37 #define ROCKCHIP_SPI_IMR 0x002c
38 #define ROCKCHIP_SPI_ISR 0x0030
39 #define ROCKCHIP_SPI_RISR 0x0034
40 #define ROCKCHIP_SPI_ICR 0x0038
41 #define ROCKCHIP_SPI_DMACR 0x003c
42 #define ROCKCHIP_SPI_DMATDLR 0x0040
43 #define ROCKCHIP_SPI_DMARDLR 0x0044
44 #define ROCKCHIP_SPI_VERSION 0x0048
45 #define ROCKCHIP_SPI_TXDR 0x0400
46 #define ROCKCHIP_SPI_RXDR 0x0800
47
48 /* Bit fields in CTRLR0 */
49 #define CR0_DFS_OFFSET 0
50 #define CR0_DFS_4BIT 0x0
51 #define CR0_DFS_8BIT 0x1
52 #define CR0_DFS_16BIT 0x2
53
54 #define CR0_CFS_OFFSET 2
55
56 #define CR0_SCPH_OFFSET 6
57
58 #define CR0_SCPOL_OFFSET 7
59
60 #define CR0_CSM_OFFSET 8
61 #define CR0_CSM_KEEP 0x0
62 /* ss_n be high for half sclk_out cycles */
63 #define CR0_CSM_HALF 0X1
64 /* ss_n be high for one sclk_out cycle */
65 #define CR0_CSM_ONE 0x2
66
67 /* ss_n to sclk_out delay */
68 #define CR0_SSD_OFFSET 10
69 /*
70 * The period between ss_n active and
71 * sclk_out active is half sclk_out cycles
72 */
73 #define CR0_SSD_HALF 0x0
74 /*
75 * The period between ss_n active and
76 * sclk_out active is one sclk_out cycle
77 */
78 #define CR0_SSD_ONE 0x1
79
80 #define CR0_EM_OFFSET 11
81 #define CR0_EM_LITTLE 0x0
82 #define CR0_EM_BIG 0x1
83
84 #define CR0_FBM_OFFSET 12
85 #define CR0_FBM_MSB 0x0
86 #define CR0_FBM_LSB 0x1
87
88 #define CR0_BHT_OFFSET 13
89 #define CR0_BHT_16BIT 0x0
90 #define CR0_BHT_8BIT 0x1
91
92 #define CR0_RSD_OFFSET 14
93 #define CR0_RSD_MAX 0x3
94
95 #define CR0_FRF_OFFSET 16
96 #define CR0_FRF_SPI 0x0
97 #define CR0_FRF_SSP 0x1
98 #define CR0_FRF_MICROWIRE 0x2
99
100 #define CR0_XFM_OFFSET 18
101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
102 #define CR0_XFM_TR 0x0
103 #define CR0_XFM_TO 0x1
104 #define CR0_XFM_RO 0x2
105
106 #define CR0_OPM_OFFSET 20
107 #define CR0_OPM_MASTER 0x0
108 #define CR0_OPM_SLAVE 0x1
109
110 #define CR0_MTM_OFFSET 0x21
111
112 /* Bit fields in SER, 2bit */
113 #define SER_MASK 0x3
114
115 /* Bit fields in BAUDR */
116 #define BAUDR_SCKDV_MIN 2
117 #define BAUDR_SCKDV_MAX 65534
118
119 /* Bit fields in SR, 5bit */
120 #define SR_MASK 0x1f
121 #define SR_BUSY (1 << 0)
122 #define SR_TF_FULL (1 << 1)
123 #define SR_TF_EMPTY (1 << 2)
124 #define SR_RF_EMPTY (1 << 3)
125 #define SR_RF_FULL (1 << 4)
126
127 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
128 #define INT_MASK 0x1f
129 #define INT_TF_EMPTY (1 << 0)
130 #define INT_TF_OVERFLOW (1 << 1)
131 #define INT_RF_UNDERFLOW (1 << 2)
132 #define INT_RF_OVERFLOW (1 << 3)
133 #define INT_RF_FULL (1 << 4)
134
135 /* Bit fields in ICR, 4bit */
136 #define ICR_MASK 0x0f
137 #define ICR_ALL (1 << 0)
138 #define ICR_RF_UNDERFLOW (1 << 1)
139 #define ICR_RF_OVERFLOW (1 << 2)
140 #define ICR_TF_OVERFLOW (1 << 3)
141
142 /* Bit fields in DMACR */
143 #define RF_DMA_EN (1 << 0)
144 #define TF_DMA_EN (1 << 1)
145
146 /* Driver state flags */
147 #define RXDMA (1 << 0)
148 #define TXDMA (1 << 1)
149
150 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
151 #define MAX_SCLK_OUT 50000000U
152
153 /*
154 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
155 * the controller seems to hang when given 0x10000, so stick with this for now.
156 */
157 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
158
159 #define ROCKCHIP_SPI_MAX_CS_NUM 2
160 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
161 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
162
163 struct rockchip_spi {
164 struct device *dev;
165
166 struct clk *spiclk;
167 struct clk *apb_pclk;
168
169 void __iomem *regs;
170 dma_addr_t dma_addr_rx;
171 dma_addr_t dma_addr_tx;
172
173 const void *tx;
174 void *rx;
175 unsigned int tx_left;
176 unsigned int rx_left;
177
178 atomic_t state;
179
180 /*depth of the FIFO buffer */
181 u32 fifo_len;
182 /* frequency of spiclk */
183 u32 freq;
184
185 u8 n_bytes;
186 u8 rsd;
187
188 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
189
190 bool slave_abort;
191 };
192
spi_enable_chip(struct rockchip_spi * rs,bool enable)193 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
194 {
195 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
196 }
197
wait_for_idle(struct rockchip_spi * rs)198 static inline void wait_for_idle(struct rockchip_spi *rs)
199 {
200 unsigned long timeout = jiffies + msecs_to_jiffies(5);
201
202 do {
203 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
204 return;
205 } while (!time_after(jiffies, timeout));
206
207 dev_warn(rs->dev, "spi controller is in busy state!\n");
208 }
209
get_fifo_len(struct rockchip_spi * rs)210 static u32 get_fifo_len(struct rockchip_spi *rs)
211 {
212 u32 ver;
213
214 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
215
216 switch (ver) {
217 case ROCKCHIP_SPI_VER2_TYPE1:
218 case ROCKCHIP_SPI_VER2_TYPE2:
219 return 64;
220 default:
221 return 32;
222 }
223 }
224
rockchip_spi_set_cs(struct spi_device * spi,bool enable)225 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
226 {
227 struct spi_controller *ctlr = spi->controller;
228 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
229 bool cs_asserted = !enable;
230
231 /* Return immediately for no-op */
232 if (cs_asserted == rs->cs_asserted[spi->chip_select])
233 return;
234
235 if (cs_asserted) {
236 /* Keep things powered as long as CS is asserted */
237 pm_runtime_get_sync(rs->dev);
238
239 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
240 BIT(spi->chip_select));
241 } else {
242 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
243 BIT(spi->chip_select));
244
245 /* Drop reference from when we first asserted CS */
246 pm_runtime_put(rs->dev);
247 }
248
249 rs->cs_asserted[spi->chip_select] = cs_asserted;
250 }
251
rockchip_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)252 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
253 struct spi_message *msg)
254 {
255 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
256
257 /* stop running spi transfer
258 * this also flushes both rx and tx fifos
259 */
260 spi_enable_chip(rs, false);
261
262 /* make sure all interrupts are masked */
263 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
264
265 if (atomic_read(&rs->state) & TXDMA)
266 dmaengine_terminate_async(ctlr->dma_tx);
267
268 if (atomic_read(&rs->state) & RXDMA)
269 dmaengine_terminate_async(ctlr->dma_rx);
270 }
271
rockchip_spi_pio_writer(struct rockchip_spi * rs)272 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
273 {
274 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
275 u32 words = min(rs->tx_left, tx_free);
276
277 rs->tx_left -= words;
278 for (; words; words--) {
279 u32 txw;
280
281 if (rs->n_bytes == 1)
282 txw = *(u8 *)rs->tx;
283 else
284 txw = *(u16 *)rs->tx;
285
286 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
287 rs->tx += rs->n_bytes;
288 }
289 }
290
rockchip_spi_pio_reader(struct rockchip_spi * rs)291 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
292 {
293 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
294 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
295
296 /* the hardware doesn't allow us to change fifo threshold
297 * level while spi is enabled, so instead make sure to leave
298 * enough words in the rx fifo to get the last interrupt
299 * exactly when all words have been received
300 */
301 if (rx_left) {
302 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
303
304 if (rx_left < ftl) {
305 rx_left = ftl;
306 words = rs->rx_left - rx_left;
307 }
308 }
309
310 rs->rx_left = rx_left;
311 for (; words; words--) {
312 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
313
314 if (!rs->rx)
315 continue;
316
317 if (rs->n_bytes == 1)
318 *(u8 *)rs->rx = (u8)rxw;
319 else
320 *(u16 *)rs->rx = (u16)rxw;
321 rs->rx += rs->n_bytes;
322 }
323 }
324
rockchip_spi_isr(int irq,void * dev_id)325 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
326 {
327 struct spi_controller *ctlr = dev_id;
328 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
329
330 if (rs->tx_left)
331 rockchip_spi_pio_writer(rs);
332
333 rockchip_spi_pio_reader(rs);
334 if (!rs->rx_left) {
335 spi_enable_chip(rs, false);
336 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
337 spi_finalize_current_transfer(ctlr);
338 }
339
340 return IRQ_HANDLED;
341 }
342
rockchip_spi_prepare_irq(struct rockchip_spi * rs,struct spi_transfer * xfer)343 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
344 struct spi_transfer *xfer)
345 {
346 rs->tx = xfer->tx_buf;
347 rs->rx = xfer->rx_buf;
348 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
349 rs->rx_left = xfer->len / rs->n_bytes;
350
351 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
352 spi_enable_chip(rs, true);
353
354 if (rs->tx_left)
355 rockchip_spi_pio_writer(rs);
356
357 /* 1 means the transfer is in progress */
358 return 1;
359 }
360
rockchip_spi_dma_rxcb(void * data)361 static void rockchip_spi_dma_rxcb(void *data)
362 {
363 struct spi_controller *ctlr = data;
364 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
365 int state = atomic_fetch_andnot(RXDMA, &rs->state);
366
367 if (state & TXDMA && !rs->slave_abort)
368 return;
369
370 spi_enable_chip(rs, false);
371 spi_finalize_current_transfer(ctlr);
372 }
373
rockchip_spi_dma_txcb(void * data)374 static void rockchip_spi_dma_txcb(void *data)
375 {
376 struct spi_controller *ctlr = data;
377 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
378 int state = atomic_fetch_andnot(TXDMA, &rs->state);
379
380 if (state & RXDMA && !rs->slave_abort)
381 return;
382
383 /* Wait until the FIFO data completely. */
384 wait_for_idle(rs);
385
386 spi_enable_chip(rs, false);
387 spi_finalize_current_transfer(ctlr);
388 }
389
rockchip_spi_calc_burst_size(u32 data_len)390 static u32 rockchip_spi_calc_burst_size(u32 data_len)
391 {
392 u32 i;
393
394 /* burst size: 1, 2, 4, 8 */
395 for (i = 1; i < 8; i <<= 1) {
396 if (data_len & i)
397 break;
398 }
399
400 return i;
401 }
402
rockchip_spi_prepare_dma(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)403 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
404 struct spi_controller *ctlr, struct spi_transfer *xfer)
405 {
406 struct dma_async_tx_descriptor *rxdesc, *txdesc;
407
408 atomic_set(&rs->state, 0);
409
410 rxdesc = NULL;
411 if (xfer->rx_buf) {
412 struct dma_slave_config rxconf = {
413 .direction = DMA_DEV_TO_MEM,
414 .src_addr = rs->dma_addr_rx,
415 .src_addr_width = rs->n_bytes,
416 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len /
417 rs->n_bytes),
418 };
419
420 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
421
422 rxdesc = dmaengine_prep_slave_sg(
423 ctlr->dma_rx,
424 xfer->rx_sg.sgl, xfer->rx_sg.nents,
425 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
426 if (!rxdesc)
427 return -EINVAL;
428
429 rxdesc->callback = rockchip_spi_dma_rxcb;
430 rxdesc->callback_param = ctlr;
431 }
432
433 txdesc = NULL;
434 if (xfer->tx_buf) {
435 struct dma_slave_config txconf = {
436 .direction = DMA_MEM_TO_DEV,
437 .dst_addr = rs->dma_addr_tx,
438 .dst_addr_width = rs->n_bytes,
439 .dst_maxburst = rs->fifo_len / 4,
440 };
441
442 dmaengine_slave_config(ctlr->dma_tx, &txconf);
443
444 txdesc = dmaengine_prep_slave_sg(
445 ctlr->dma_tx,
446 xfer->tx_sg.sgl, xfer->tx_sg.nents,
447 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
448 if (!txdesc) {
449 if (rxdesc)
450 dmaengine_terminate_sync(ctlr->dma_rx);
451 return -EINVAL;
452 }
453
454 txdesc->callback = rockchip_spi_dma_txcb;
455 txdesc->callback_param = ctlr;
456 }
457
458 /* rx must be started before tx due to spi instinct */
459 if (rxdesc) {
460 atomic_or(RXDMA, &rs->state);
461 dmaengine_submit(rxdesc);
462 dma_async_issue_pending(ctlr->dma_rx);
463 }
464
465 spi_enable_chip(rs, true);
466
467 if (txdesc) {
468 atomic_or(TXDMA, &rs->state);
469 dmaengine_submit(txdesc);
470 dma_async_issue_pending(ctlr->dma_tx);
471 }
472
473 /* 1 means the transfer is in progress */
474 return 1;
475 }
476
rockchip_spi_config(struct rockchip_spi * rs,struct spi_device * spi,struct spi_transfer * xfer,bool use_dma,bool slave_mode)477 static int rockchip_spi_config(struct rockchip_spi *rs,
478 struct spi_device *spi, struct spi_transfer *xfer,
479 bool use_dma, bool slave_mode)
480 {
481 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
482 | CR0_BHT_8BIT << CR0_BHT_OFFSET
483 | CR0_SSD_ONE << CR0_SSD_OFFSET
484 | CR0_EM_BIG << CR0_EM_OFFSET;
485 u32 cr1;
486 u32 dmacr = 0;
487
488 if (slave_mode)
489 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
490 rs->slave_abort = false;
491
492 cr0 |= rs->rsd << CR0_RSD_OFFSET;
493 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
494 if (spi->mode & SPI_LSB_FIRST)
495 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
496
497 if (xfer->rx_buf && xfer->tx_buf)
498 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
499 else if (xfer->rx_buf)
500 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
501 else if (use_dma)
502 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
503
504 switch (xfer->bits_per_word) {
505 case 4:
506 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
507 cr1 = xfer->len - 1;
508 break;
509 case 8:
510 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
511 cr1 = xfer->len - 1;
512 break;
513 case 16:
514 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
515 cr1 = xfer->len / 2 - 1;
516 break;
517 default:
518 /* we only whitelist 4, 8 and 16 bit words in
519 * ctlr->bits_per_word_mask, so this shouldn't
520 * happen
521 */
522 dev_err(rs->dev, "unknown bits per word: %d\n",
523 xfer->bits_per_word);
524 return -EINVAL;
525 }
526
527 if (use_dma) {
528 if (xfer->tx_buf)
529 dmacr |= TF_DMA_EN;
530 if (xfer->rx_buf)
531 dmacr |= RF_DMA_EN;
532 }
533
534 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
535 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
536
537 /* unfortunately setting the fifo threshold level to generate an
538 * interrupt exactly when the fifo is full doesn't seem to work,
539 * so we need the strict inequality here
540 */
541 if (xfer->len < rs->fifo_len)
542 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
543 else
544 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
545
546 writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR);
547 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
548 rs->regs + ROCKCHIP_SPI_DMARDLR);
549 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
550
551 /* the hardware only supports an even clock divisor, so
552 * round divisor = spiclk / speed up to nearest even number
553 * so that the resulting speed is <= the requested speed
554 */
555 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
556 rs->regs + ROCKCHIP_SPI_BAUDR);
557
558 return 0;
559 }
560
rockchip_spi_max_transfer_size(struct spi_device * spi)561 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
562 {
563 return ROCKCHIP_SPI_MAX_TRANLEN;
564 }
565
rockchip_spi_slave_abort(struct spi_controller * ctlr)566 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
567 {
568 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
569
570 if (atomic_read(&rs->state) & RXDMA)
571 dmaengine_terminate_sync(ctlr->dma_rx);
572 if (atomic_read(&rs->state) & TXDMA)
573 dmaengine_terminate_sync(ctlr->dma_tx);
574 atomic_set(&rs->state, 0);
575 spi_enable_chip(rs, false);
576 rs->slave_abort = true;
577 complete(&ctlr->xfer_completion);
578
579 return 0;
580 }
581
rockchip_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)582 static int rockchip_spi_transfer_one(
583 struct spi_controller *ctlr,
584 struct spi_device *spi,
585 struct spi_transfer *xfer)
586 {
587 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
588 int ret;
589 bool use_dma;
590
591 /* Zero length transfers won't trigger an interrupt on completion */
592 if (!xfer->len) {
593 spi_finalize_current_transfer(ctlr);
594 return 1;
595 }
596
597 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
598 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
599
600 if (!xfer->tx_buf && !xfer->rx_buf) {
601 dev_err(rs->dev, "No buffer for transfer\n");
602 return -EINVAL;
603 }
604
605 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
606 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
607 return -EINVAL;
608 }
609
610 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
611
612 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
613
614 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
615 if (ret)
616 return ret;
617
618 if (use_dma)
619 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
620
621 return rockchip_spi_prepare_irq(rs, xfer);
622 }
623
rockchip_spi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)624 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
625 struct spi_device *spi,
626 struct spi_transfer *xfer)
627 {
628 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
629 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
630
631 /* if the numbor of spi words to transfer is less than the fifo
632 * length we can just fill the fifo and wait for a single irq,
633 * so don't bother setting up dma
634 */
635 return xfer->len / bytes_per_word >= rs->fifo_len;
636 }
637
rockchip_spi_probe(struct platform_device * pdev)638 static int rockchip_spi_probe(struct platform_device *pdev)
639 {
640 int ret;
641 struct rockchip_spi *rs;
642 struct spi_controller *ctlr;
643 struct resource *mem;
644 struct device_node *np = pdev->dev.of_node;
645 u32 rsd_nsecs, num_cs;
646 bool slave_mode;
647
648 slave_mode = of_property_read_bool(np, "spi-slave");
649
650 if (slave_mode)
651 ctlr = spi_alloc_slave(&pdev->dev,
652 sizeof(struct rockchip_spi));
653 else
654 ctlr = spi_alloc_master(&pdev->dev,
655 sizeof(struct rockchip_spi));
656
657 if (!ctlr)
658 return -ENOMEM;
659
660 platform_set_drvdata(pdev, ctlr);
661
662 rs = spi_controller_get_devdata(ctlr);
663 ctlr->slave = slave_mode;
664
665 /* Get basic io resource and map it */
666 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
667 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
668 if (IS_ERR(rs->regs)) {
669 ret = PTR_ERR(rs->regs);
670 goto err_put_ctlr;
671 }
672
673 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
674 if (IS_ERR(rs->apb_pclk)) {
675 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
676 ret = PTR_ERR(rs->apb_pclk);
677 goto err_put_ctlr;
678 }
679
680 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
681 if (IS_ERR(rs->spiclk)) {
682 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
683 ret = PTR_ERR(rs->spiclk);
684 goto err_put_ctlr;
685 }
686
687 ret = clk_prepare_enable(rs->apb_pclk);
688 if (ret < 0) {
689 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
690 goto err_put_ctlr;
691 }
692
693 ret = clk_prepare_enable(rs->spiclk);
694 if (ret < 0) {
695 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
696 goto err_disable_apbclk;
697 }
698
699 spi_enable_chip(rs, false);
700
701 ret = platform_get_irq(pdev, 0);
702 if (ret < 0)
703 goto err_disable_spiclk;
704
705 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
706 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
707 if (ret)
708 goto err_disable_spiclk;
709
710 rs->dev = &pdev->dev;
711 rs->freq = clk_get_rate(rs->spiclk);
712
713 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
714 &rsd_nsecs)) {
715 /* rx sample delay is expressed in parent clock cycles (max 3) */
716 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
717 1000000000 >> 8);
718 if (!rsd) {
719 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
720 rs->freq, rsd_nsecs);
721 } else if (rsd > CR0_RSD_MAX) {
722 rsd = CR0_RSD_MAX;
723 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
724 rs->freq, rsd_nsecs,
725 CR0_RSD_MAX * 1000000000U / rs->freq);
726 }
727 rs->rsd = rsd;
728 }
729
730 rs->fifo_len = get_fifo_len(rs);
731 if (!rs->fifo_len) {
732 dev_err(&pdev->dev, "Failed to get fifo length\n");
733 ret = -EINVAL;
734 goto err_disable_spiclk;
735 }
736
737 pm_runtime_set_active(&pdev->dev);
738 pm_runtime_enable(&pdev->dev);
739
740 ctlr->auto_runtime_pm = true;
741 ctlr->bus_num = pdev->id;
742 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
743 if (slave_mode) {
744 ctlr->mode_bits |= SPI_NO_CS;
745 ctlr->slave_abort = rockchip_spi_slave_abort;
746 } else {
747 ctlr->flags = SPI_MASTER_GPIO_SS;
748 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
749 /*
750 * rk spi0 has two native cs, spi1..5 one cs only
751 * if num-cs is missing in the dts, default to 1
752 */
753 if (of_property_read_u32(np, "num-cs", &num_cs))
754 num_cs = 1;
755 ctlr->num_chipselect = num_cs;
756 ctlr->use_gpio_descriptors = true;
757 }
758 ctlr->dev.of_node = pdev->dev.of_node;
759 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
760 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
761 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
762
763 ctlr->set_cs = rockchip_spi_set_cs;
764 ctlr->transfer_one = rockchip_spi_transfer_one;
765 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
766 ctlr->handle_err = rockchip_spi_handle_err;
767
768 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
769 if (IS_ERR(ctlr->dma_tx)) {
770 /* Check tx to see if we need defer probing driver */
771 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
772 ret = -EPROBE_DEFER;
773 goto err_disable_pm_runtime;
774 }
775 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
776 ctlr->dma_tx = NULL;
777 }
778
779 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
780 if (IS_ERR(ctlr->dma_rx)) {
781 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
782 ret = -EPROBE_DEFER;
783 goto err_free_dma_tx;
784 }
785 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
786 ctlr->dma_rx = NULL;
787 }
788
789 if (ctlr->dma_tx && ctlr->dma_rx) {
790 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
791 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
792 ctlr->can_dma = rockchip_spi_can_dma;
793 }
794
795 ret = devm_spi_register_controller(&pdev->dev, ctlr);
796 if (ret < 0) {
797 dev_err(&pdev->dev, "Failed to register controller\n");
798 goto err_free_dma_rx;
799 }
800
801 return 0;
802
803 err_free_dma_rx:
804 if (ctlr->dma_rx)
805 dma_release_channel(ctlr->dma_rx);
806 err_free_dma_tx:
807 if (ctlr->dma_tx)
808 dma_release_channel(ctlr->dma_tx);
809 err_disable_pm_runtime:
810 pm_runtime_disable(&pdev->dev);
811 err_disable_spiclk:
812 clk_disable_unprepare(rs->spiclk);
813 err_disable_apbclk:
814 clk_disable_unprepare(rs->apb_pclk);
815 err_put_ctlr:
816 spi_controller_put(ctlr);
817
818 return ret;
819 }
820
rockchip_spi_remove(struct platform_device * pdev)821 static int rockchip_spi_remove(struct platform_device *pdev)
822 {
823 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
824 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
825
826 pm_runtime_get_sync(&pdev->dev);
827
828 clk_disable_unprepare(rs->spiclk);
829 clk_disable_unprepare(rs->apb_pclk);
830
831 pm_runtime_put_noidle(&pdev->dev);
832 pm_runtime_disable(&pdev->dev);
833 pm_runtime_set_suspended(&pdev->dev);
834
835 if (ctlr->dma_tx)
836 dma_release_channel(ctlr->dma_tx);
837 if (ctlr->dma_rx)
838 dma_release_channel(ctlr->dma_rx);
839
840 spi_controller_put(ctlr);
841
842 return 0;
843 }
844
845 #ifdef CONFIG_PM_SLEEP
rockchip_spi_suspend(struct device * dev)846 static int rockchip_spi_suspend(struct device *dev)
847 {
848 int ret;
849 struct spi_controller *ctlr = dev_get_drvdata(dev);
850
851 ret = spi_controller_suspend(ctlr);
852 if (ret < 0)
853 return ret;
854
855 ret = pm_runtime_force_suspend(dev);
856 if (ret < 0)
857 return ret;
858
859 pinctrl_pm_select_sleep_state(dev);
860
861 return 0;
862 }
863
rockchip_spi_resume(struct device * dev)864 static int rockchip_spi_resume(struct device *dev)
865 {
866 int ret;
867 struct spi_controller *ctlr = dev_get_drvdata(dev);
868 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
869
870 pinctrl_pm_select_default_state(dev);
871
872 ret = pm_runtime_force_resume(dev);
873 if (ret < 0)
874 return ret;
875
876 ret = spi_controller_resume(ctlr);
877 if (ret < 0) {
878 clk_disable_unprepare(rs->spiclk);
879 clk_disable_unprepare(rs->apb_pclk);
880 }
881
882 return 0;
883 }
884 #endif /* CONFIG_PM_SLEEP */
885
886 #ifdef CONFIG_PM
rockchip_spi_runtime_suspend(struct device * dev)887 static int rockchip_spi_runtime_suspend(struct device *dev)
888 {
889 struct spi_controller *ctlr = dev_get_drvdata(dev);
890 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
891
892 clk_disable_unprepare(rs->spiclk);
893 clk_disable_unprepare(rs->apb_pclk);
894
895 return 0;
896 }
897
rockchip_spi_runtime_resume(struct device * dev)898 static int rockchip_spi_runtime_resume(struct device *dev)
899 {
900 int ret;
901 struct spi_controller *ctlr = dev_get_drvdata(dev);
902 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
903
904 ret = clk_prepare_enable(rs->apb_pclk);
905 if (ret < 0)
906 return ret;
907
908 ret = clk_prepare_enable(rs->spiclk);
909 if (ret < 0)
910 clk_disable_unprepare(rs->apb_pclk);
911
912 return 0;
913 }
914 #endif /* CONFIG_PM */
915
916 static const struct dev_pm_ops rockchip_spi_pm = {
917 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
918 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
919 rockchip_spi_runtime_resume, NULL)
920 };
921
922 static const struct of_device_id rockchip_spi_dt_match[] = {
923 { .compatible = "rockchip,px30-spi", },
924 { .compatible = "rockchip,rk3036-spi", },
925 { .compatible = "rockchip,rk3066-spi", },
926 { .compatible = "rockchip,rk3188-spi", },
927 { .compatible = "rockchip,rk3228-spi", },
928 { .compatible = "rockchip,rk3288-spi", },
929 { .compatible = "rockchip,rk3308-spi", },
930 { .compatible = "rockchip,rk3328-spi", },
931 { .compatible = "rockchip,rk3368-spi", },
932 { .compatible = "rockchip,rk3399-spi", },
933 { .compatible = "rockchip,rv1108-spi", },
934 { },
935 };
936 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
937
938 static struct platform_driver rockchip_spi_driver = {
939 .driver = {
940 .name = DRIVER_NAME,
941 .pm = &rockchip_spi_pm,
942 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
943 },
944 .probe = rockchip_spi_probe,
945 .remove = rockchip_spi_remove,
946 };
947
948 module_platform_driver(rockchip_spi_driver);
949
950 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
951 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
952 MODULE_LICENSE("GPL v2");
953