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Searched refs:SSPP_DMA1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
113 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
197 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
434 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
Dmdp5_ctl.c297 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); in mdp_ctl_blend_mask()
320 case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3; in mdp_ctl_blend_ext_mask()
448 case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h76 SSPP_DMA1 = 8, enumerator
546 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); in __offset_PIPE()
Dmdp5_kms.c730 SSPP_DMA0, SSPP_DMA1, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c147 status->sspp[SSPP_DMA1] = (value >> 22) & 0x3; in dpu_hw_get_danger_status()
244 status->sspp[SSPP_DMA1] = (value >> 22) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c168 case SSPP_DMA1: in dpu_hw_ctl_get_bitmask_sspp()
443 case SSPP_DMA1: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h118 SSPP_DMA1, enumerator
Ddpu_hw_catalog.c352 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
368 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,