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Searched refs:SSPP_RGB1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
114 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
198 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
291 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
358 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
435 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
643 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
Dmdp5_ctl.c294 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage); in mdp_ctl_blend_mask()
317 case SSPP_RGB1: return MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3; in mdp_ctl_blend_ext_mask()
445 case SSPP_RGB1: return MDP5_CTL_FLUSH_RGB1; in mdp_ctl_flush_mask_pipe()
Dmdp5_kms.h214 case SSPP_RGB1: in pipe2nclients()
Dmdp5.xml.h73 SSPP_RGB1 = 5, enumerator
543 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]); in __offset_PIPE()
Dmdp5_kms.c724 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c143 status->sspp[SSPP_RGB1] = (value >> 14) & 0x3; in dpu_hw_get_danger_status()
240 status->sspp[SSPP_RGB1] = (value >> 14) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c156 case SSPP_RGB1: in dpu_hw_ctl_get_bitmask_sspp()
423 case SSPP_RGB1: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h114 SSPP_RGB1, enumerator