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Searched refs:SSPP_RGB3 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c145 status->sspp[SSPP_RGB3] = (value >> 18) & 0x3; in dpu_hw_get_danger_status()
242 status->sspp[SSPP_RGB3] = (value >> 18) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c162 case SSPP_RGB3: in dpu_hw_ctl_get_bitmask_sspp()
431 case SSPP_RGB3: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h116 SSPP_RGB3, enumerator
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.c299 case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage); in mdp_ctl_blend_mask()
322 case SSPP_RGB3: return MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3; in mdp_ctl_blend_ext_mask()
450 case SSPP_RGB3: return MDP5_CTL_FLUSH_RGB3; in mdp_ctl_flush_mask_pipe()
Dmdp5_kms.h216 case SSPP_RGB3: in pipe2nclients()
Dmdp5_cfg.c199 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
436 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
Dmdp5.xml.h78 SSPP_RGB3 = 10, enumerator
548 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]); in __offset_PIPE()
Dmdp5_kms.c724 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, in hwpipe_init() enumerator