Searched refs:SW_MODE (Results 1 – 7 of 7) sorted by relevance
| /drivers/mtd/devices/ |
| D | spear_smi.c | 60 #define SW_MODE (0x1 << 28) /* enables SW Mode */ macro
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
389 writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_write_enable()
461 writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1); in spear_smi_erase_sector()
577 val &= ~(SW_MODE | WB_MODE); in spear_mtd_read()
635 writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_cpy_toio()
759 writel(val | SW_MODE, dev->io_base + SMI_CR1); in spear_smi_probe_flash()
784 writel(val & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_probe_flash()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.h | 269 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
464 type SW_MODE;\
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| D | dcn10_hubp.c | 157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
1020 SW_MODE, &s->sw_mode); in hubp1_read_state_common()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hubp.h | 69 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
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| D | dcn30_hubp.c | 335 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 321 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
1223 SW_MODE, &s->sw_mode); in hubp2_read_state_common()
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| /drivers/gpu/drm/amd/include/ |
| D | navi10_enum.h | 1561 typedef enum SW_MODE { enum
1578 } SW_MODE; typedef
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