| /drivers/block/drbd/ |
| D | drbd_state.h | 40 #define NS2(T1, S1, T2, S2) \ argument
41 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
43 ({ union drbd_state val; val.i = 0; val.T1 = (S1); \
45 #define NS3(T1, S1, T2, S2, T3, S3) \ argument
46 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
48 ({ union drbd_state val; val.i = 0; val.T1 = (S1); \
53 #define _NS2(D, T1, S1, T2, S2) \ argument
54 D, ({ union drbd_state __ns; __ns = drbd_read_state(D); __ns.T1 = (S1); \
56 #define _NS3(D, T1, S1, T2, S2, T3, S3) \ argument
57 D, ({ union drbd_state __ns; __ns = drbd_read_state(D); __ns.T1 = (S1); \
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| /drivers/clk/baikal-t1/ |
| D | Kconfig | 3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
31 bool "Baikal-T1 CCU Dividers support"
37 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
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| /drivers/iio/pressure/ |
| D | bmp280-core.c | 57 u16 T1; member
129 enum { T1, T2, T3 }; enumerator
174 calib->T1 = le16_to_cpu(t_buf[T1]); in bmp280_read_calib()
292 var1 = (((adc_temp >> 3) - ((s32)calib->T1 << 1)) * in bmp280_compensate_temp()
294 var2 = (((((adc_temp >> 4) - ((s32)calib->T1)) * in bmp280_compensate_temp()
295 ((adc_temp >> 4) - ((s32)calib->T1))) >> 12) * in bmp280_compensate_temp()
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| /drivers/bus/ |
| D | Kconfig | 42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
57 bool "Baikal-T1 AXI-bus driver"
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
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| /drivers/net/wan/ |
| D | farsync.h | 193 #define T1 5 macro
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| D | Kconfig | 64 tristate "LanMedia Corp. SSI/V.35, T1/E1, HSSI, T3 boards"
74 box directly to a T1 or E1 circuit.
288 in T1 or E1 mode.
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| D | farsync.c | 1697 if (info->framing == T1) in set_conf_from_info()
1890 FST_WRW(card, portConfig[i].lineInterface, T1); in fst_set_iface()
1891 port->hwif = T1; in fst_set_iface()
1937 case T1: in fst_get_iface()
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| /drivers/memory/ |
| D | Kconfig | 70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
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| /drivers/spi/ |
| D | Kconfig | 256 tristate "Baikal-T1 SPI driver for DW SPI core"
260 Baikal-T1 SoC is equipped with three DW APB SSI-based MMIO SPI
263 part of the Baikal-T1 System Boot Controller has got a very
270 bool "Directly mapped Baikal-T1 Boot SPI flash support"
274 Baikal-T1 System Boot Controller. It is a 16MB MMIO region, which
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| /drivers/mtd/maps/ |
| D | Kconfig | 79 bool "Baikal-T1 Boot ROMs OF-based physical memory map handling"
86 This provides some extra DT physmap parsing for the Baikal-T1
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| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g5.c | 700 #define T1 89 macro
702 SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
703 SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
704 PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
705 FUNC_GROUP_DECL(NDCD1, T1);
929 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
2086 ASPEED_PINCTRL_PIN(T1),
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| D | pinctrl-aspeed-g4.c | 636 #define T1 79 macro
637 SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
2085 ASPEED_PINCTRL_PIN(T1),
2458 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
2459 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
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| /drivers/net/phy/ |
| D | Kconfig | 215 tristate "Microchip T1 PHYs"
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| /drivers/net/ppp/ |
| D | Kconfig | 172 are often used for high-speed leased lines like T1/E1.
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| /drivers/tty/ |
| D | n_gsm.c | 60 #define T1 10 /* 100mS */ macro
66 #define T1 100 macro
2386 gsm->t1 = T1; in gsm_alloc_mux()
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| /drivers/hwmon/ |
| D | Kconfig | 418 tristate "Baikal-T1 Process, Voltage, Temperature sensor driver"
421 If you say yes here you get support for Baikal-T1 PVT sensor
428 bool "Enable Baikal-T1 PVT sensor alarms"
431 Baikal-T1 PVT IP-block provides threshold registers for each
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