Home
last modified time | relevance | path

Searched refs:TB_CFG_PORT (Results 1 – 11 of 11) sorted by relevance

/drivers/thunderbolt/
Dusb4.c225 if (tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_check_wakes()
247 if (tb_port_read(port, &val, TB_CFG_PORT, in link_is_usb4()
398 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); in usb4_switch_lane_bonding_possible()
432 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
446 ret = tb_port_write(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
849 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
854 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
869 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
874 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
885 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_port_set_configured()
[all …]
Dswitch.c519 res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); in tb_port_state()
621 TB_CFG_PORT, ADP_CS_4, 1); in tb_port_add_nfc_credits()
636 ret = tb_port_read(port, &data, TB_CFG_PORT, ADP_CS_5, 1); in tb_port_set_initial_credits()
643 return tb_port_write(port, &data, TB_CFG_PORT, ADP_CS_5, 1); in tb_port_set_initial_credits()
684 ret = tb_port_read(port, &phy, TB_CFG_PORT, in __tb_port_enable()
694 return tb_port_write(port, &phy, TB_CFG_PORT, in __tb_port_enable()
733 res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); in tb_init_port()
919 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_speed()
937 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_width()
954 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_is_width_supported()
[all …]
Dcap.c58 tb_port_read(port, &dummy, TB_CFG_PORT, 0, 1); in tb_port_dummy_read()
80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap()
99 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in __tb_port_find_cap()
Dtunnel.c269 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
276 ret = tb_port_write(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
282 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
444 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
449 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
455 ret = tb_port_write(out, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
503 return tb_port_write(in, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
560 ret = tb_port_read(in, &val, TB_CFG_PORT, in tb_dp_consumed_bandwidth()
580 ret = tb_port_read(in, &val, TB_CFG_PORT, in tb_dp_consumed_bandwidth()
Dtmu.c90 ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1); in tb_port_tmu_write()
97 return tb_port_write(port, &data, TB_CFG_PORT, in tb_port_tmu_write()
123 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_unidirectional()
Ddebugfs.c149 ret = tb_port_write(port, &val, TB_CFG_PORT, offset, 1); in regs_write()
265 ret = tb_port_read(port, data, TB_CFG_PORT, cap + offset, in cap_show()
296 ret = tb_port_read(port, &header, TB_CFG_PORT, cap, 1); in port_cap_show()
332 ret = tb_port_read(port, (u32 *)&header + 1, TB_CFG_PORT, in port_cap_show()
385 ret = tb_port_read(port, data, TB_CFG_PORT, 0, ARRAY_SIZE(data)); in port_basic_regs_show()
Ddma_port.c96 .space = TB_CFG_PORT, in dma_port_read()
137 .space = TB_CFG_PORT, in dma_port_write()
Dicm.c1812 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1815 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1829 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1834 ret = pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
1841 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1844 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1849 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1854 return pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
Dtb_msgs.h17 TB_CFG_PORT = 1, enumerator
Deeprom.c356 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); in tb_drom_parse_entry_port()
Dctl.c957 if (space == TB_CFG_PORT && in tb_cfg_get_error()