1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __TEGRA_VI_H__ 7 #define __TEGRA_VI_H__ 8 9 #include <linux/host1x.h> 10 #include <linux/list.h> 11 12 #include <linux/mutex.h> 13 #include <linux/spinlock.h> 14 #include <linux/wait.h> 15 16 #include <media/media-entity.h> 17 #include <media/v4l2-async.h> 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-dev.h> 21 #include <media/v4l2-subdev.h> 22 #include <media/videobuf2-v4l2.h> 23 24 #define TEGRA_MIN_WIDTH 32U 25 #define TEGRA_MAX_WIDTH 32768U 26 #define TEGRA_MIN_HEIGHT 32U 27 #define TEGRA_MAX_HEIGHT 32768U 28 29 #define TEGRA_DEF_WIDTH 1920 30 #define TEGRA_DEF_HEIGHT 1080 31 #define TEGRA_IMAGE_FORMAT_DEF 32 32 33 #define MAX_FORMAT_NUM 64 34 35 enum tegra_vi_pg_mode { 36 TEGRA_VI_PG_DISABLED = 0, 37 TEGRA_VI_PG_DIRECT, 38 TEGRA_VI_PG_PATCH, 39 }; 40 41 /** 42 * struct tegra_vi_ops - Tegra VI operations 43 * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up 44 * VI for capture and runs capture start and capture finish 45 * kthreads for capturing frames to buffer and returns them back. 46 * @vi_stop_streaming: stops media pipeline and subdevice streaming and returns 47 * back any queued buffers. 48 */ 49 struct tegra_vi_ops { 50 int (*vi_start_streaming)(struct vb2_queue *vq, u32 count); 51 void (*vi_stop_streaming)(struct vb2_queue *vq); 52 }; 53 54 /** 55 * struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure 56 * 57 * @video_formats: supported video formats 58 * @nformats: total video formats 59 * @ops: vi operations 60 * @hw_revision: VI hw_revision 61 * @vi_max_channels: supported max streaming channels 62 * @vi_max_clk_hz: VI clock max frequency 63 */ 64 struct tegra_vi_soc { 65 const struct tegra_video_format *video_formats; 66 const unsigned int nformats; 67 const struct tegra_vi_ops *ops; 68 u32 hw_revision; 69 unsigned int vi_max_channels; 70 unsigned int vi_max_clk_hz; 71 }; 72 73 /** 74 * struct tegra_vi - NVIDIA Tegra Video Input device structure 75 * 76 * @dev: device struct 77 * @client: host1x_client struct 78 * @iomem: register base 79 * @clk: main clock for VI block 80 * @vdd: vdd regulator for VI hardware, normally it is avdd_dsi_csi 81 * @soc: pointer to SoC data structure 82 * @ops: vi operations 83 * @vi_chans: list head for VI channels 84 */ 85 struct tegra_vi { 86 struct device *dev; 87 struct host1x_client client; 88 void __iomem *iomem; 89 struct clk *clk; 90 struct regulator *vdd; 91 const struct tegra_vi_soc *soc; 92 const struct tegra_vi_ops *ops; 93 struct list_head vi_chans; 94 }; 95 96 /** 97 * struct tegra_vi_graph_entity - Entity in the video graph 98 * 99 * @asd: subdev asynchronous registration information 100 * @entity: media entity from the corresponding V4L2 subdev 101 * @subdev: V4L2 subdev 102 */ 103 struct tegra_vi_graph_entity { 104 struct v4l2_async_subdev asd; 105 struct media_entity *entity; 106 struct v4l2_subdev *subdev; 107 }; 108 109 /** 110 * struct tegra_vi_channel - Tegra video channel 111 * 112 * @list: list head for this entry 113 * @video: V4L2 video device associated with the video channel 114 * @video_lock: protects the @format and @queue fields 115 * @pad: media pad for the video device entity 116 * 117 * @vi: Tegra video input device structure 118 * @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture 119 * start condition with hardware frame start events through host1x 120 * syncpoint counters. 121 * @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write 122 * ack trigger condition with hardware memory write done at end of 123 * frame through host1x syncpoint counters. 124 * @sp_incr_lock: protects cpu syncpoint increment. 125 * 126 * @kthread_start_capture: kthread to start capture of single frame when 127 * vb buffer is available. This thread programs VI CSI hardware 128 * for single frame capture and waits for frame start event from 129 * the hardware. On receiving frame start event, it wakes up 130 * kthread_finish_capture thread to wait for finishing frame data 131 * write to the memory. In case of missing frame start event, this 132 * thread returns buffer back to vb with VB2_BUF_STATE_ERROR. 133 * @start_wait: waitqueue for starting frame capture when buffer is available. 134 * @kthread_finish_capture: kthread to finish the buffer capture and return to. 135 * This thread is woken up by kthread_start_capture on receiving 136 * frame start event from the hardware and this thread waits for 137 * MW_ACK_DONE event which indicates completion of writing frame 138 * data to the memory. On receiving MW_ACK_DONE event, buffer is 139 * returned back to vb with VB2_BUF_STATE_DONE and in case of 140 * missing MW_ACK_DONE event, buffer is returned back to vb with 141 * VB2_BUF_STATE_ERROR. 142 * @done_wait: waitqueue for finishing capture data writes to memory. 143 * 144 * @format: active V4L2 pixel format 145 * @fmtinfo: format information corresponding to the active @format 146 * @queue: vb2 buffers queue 147 * @sequence: V4L2 buffers sequence number 148 * 149 * @capture: list of queued buffers for capture 150 * @start_lock: protects the capture queued list 151 * @done: list of capture done queued buffers 152 * @done_lock: protects the capture done queue list 153 * 154 * @portno: VI channel port number 155 * @of_node: device node of VI channel 156 * 157 * @ctrl_handler: V4L2 control handler of this video channel 158 * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats 159 * @tpg_fmts_bitmap: a bitmap for supported TPG formats 160 * @pg_mode: test pattern generator mode (disabled/direct/patch) 161 * @notifier: V4L2 asynchronous subdevs notifier 162 */ 163 struct tegra_vi_channel { 164 struct list_head list; 165 struct video_device video; 166 /* protects the @format and @queue fields */ 167 struct mutex video_lock; 168 struct media_pad pad; 169 170 struct tegra_vi *vi; 171 struct host1x_syncpt *frame_start_sp; 172 struct host1x_syncpt *mw_ack_sp; 173 /* protects the cpu syncpoint increment */ 174 spinlock_t sp_incr_lock; 175 176 struct task_struct *kthread_start_capture; 177 wait_queue_head_t start_wait; 178 struct task_struct *kthread_finish_capture; 179 wait_queue_head_t done_wait; 180 181 struct v4l2_pix_format format; 182 const struct tegra_video_format *fmtinfo; 183 struct vb2_queue queue; 184 u32 sequence; 185 186 struct list_head capture; 187 /* protects the capture queued list */ 188 spinlock_t start_lock; 189 struct list_head done; 190 /* protects the capture done queue list */ 191 spinlock_t done_lock; 192 193 unsigned char portno; 194 struct device_node *of_node; 195 196 struct v4l2_ctrl_handler ctrl_handler; 197 DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); 198 DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); 199 enum tegra_vi_pg_mode pg_mode; 200 201 struct v4l2_async_notifier notifier; 202 }; 203 204 /** 205 * struct tegra_channel_buffer - video channel buffer 206 * 207 * @buf: vb2 buffer base object 208 * @queue: buffer list entry in the channel queued buffers list 209 * @chan: channel that uses the buffer 210 * @addr: Tegra IOVA buffer address for VI output 211 * @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding 212 * to the capture buffer. 213 */ 214 struct tegra_channel_buffer { 215 struct vb2_v4l2_buffer buf; 216 struct list_head queue; 217 struct tegra_vi_channel *chan; 218 dma_addr_t addr; 219 u32 mw_ack_sp_thresh; 220 }; 221 222 /* 223 * VI channel input data type enum. 224 * These data type enum value gets programmed into corresponding Tegra VI 225 * channel register bits. 226 */ 227 enum tegra_image_dt { 228 TEGRA_IMAGE_DT_YUV420_8 = 24, 229 TEGRA_IMAGE_DT_YUV420_10, 230 231 TEGRA_IMAGE_DT_YUV420CSPS_8 = 28, 232 TEGRA_IMAGE_DT_YUV420CSPS_10, 233 TEGRA_IMAGE_DT_YUV422_8, 234 TEGRA_IMAGE_DT_YUV422_10, 235 TEGRA_IMAGE_DT_RGB444, 236 TEGRA_IMAGE_DT_RGB555, 237 TEGRA_IMAGE_DT_RGB565, 238 TEGRA_IMAGE_DT_RGB666, 239 TEGRA_IMAGE_DT_RGB888, 240 241 TEGRA_IMAGE_DT_RAW6 = 40, 242 TEGRA_IMAGE_DT_RAW7, 243 TEGRA_IMAGE_DT_RAW8, 244 TEGRA_IMAGE_DT_RAW10, 245 TEGRA_IMAGE_DT_RAW12, 246 TEGRA_IMAGE_DT_RAW14, 247 }; 248 249 /** 250 * struct tegra_video_format - Tegra video format description 251 * 252 * @img_dt: image data type 253 * @bit_width: format width in bits per component 254 * @code: media bus format code 255 * @bpp: bytes per pixel (when stored in memory) 256 * @img_fmt: image format 257 * @fourcc: V4L2 pixel format FCC identifier 258 */ 259 struct tegra_video_format { 260 enum tegra_image_dt img_dt; 261 unsigned int bit_width; 262 unsigned int code; 263 unsigned int bpp; 264 u32 img_fmt; 265 u32 fourcc; 266 }; 267 268 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 269 extern const struct tegra_vi_soc tegra210_vi_soc; 270 #endif 271 272 struct v4l2_subdev * 273 tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); 274 struct v4l2_subdev * 275 tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); 276 int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); 277 void tegra_channel_release_buffers(struct tegra_vi_channel *chan, 278 enum vb2_buffer_state state); 279 void tegra_channels_cleanup(struct tegra_vi *vi); 280 #endif 281