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Searched refs:UMC_BASE__INST2_SEG0 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h785 #define UMC_BASE__INST2_SEG0 0 macro
Dnavi12_ip_offset.h1005 #define UMC_BASE__INST2_SEG0 0x00094000 macro
Dvega20_ip_offset.h854 #define UMC_BASE__INST2_SEG0 0 macro
Dnavi14_ip_offset.h1005 #define UMC_BASE__INST2_SEG0 0x00094000 macro
Dsienna_cichlid_ip_offset.h1054 #define UMC_BASE__INST2_SEG0 0x00094000 macro
Dvega10_ip_offset.h1097 #define UMC_BASE__INST2_SEG0 0 macro
Drenoir_ip_offset.h1255 #define UMC_BASE__INST2_SEG0 0 macro
Darct_ip_offset.h1439 #define UMC_BASE__INST2_SEG0 0x00013300 macro