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Searched refs:UVD_CGC_CTRL__CLK_OFF_DELAY_MASK (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h443 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK … macro
Duvd_4_0_sh_mask.h34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L macro
Duvd_4_2_sh_mask.h225 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 macro
Duvd_3_1_sh_mask.h225 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 macro
Duvd_5_0_sh_mask.h247 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 macro
Duvd_6_0_sh_mask.h249 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c210 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v3_1_set_dcm()
Duvd_v4_2.c608 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v4_2_set_dcm()
Duvd_v5_0.c654 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1314 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1589 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h936 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK … macro
Dvcn_2_5_sh_mask.h2004 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK … macro
Dvcn_2_0_0_sh_mask.h1955 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK … macro
Dvcn_3_0_0_sh_mask.h2734 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK … macro