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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c658 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
745 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg()
754 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v5_0_enable_mgcg()
822 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v5_0_get_clockgating_state()
Duvd_v3_1.c211 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v3_1_set_dcm()
604 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v3_1_enable_mgcg()
613 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c585 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg()
594 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v4_2_enable_mgcg()
609 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v4_2_set_dcm()
Duvd_v6_0.c1318 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
1408 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg()
1417 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in uvd_v6_0_enable_mgcg()
1490 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) in uvd_v6_0_get_clockgating_state()
Duvd_v7_0.c844 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); in uvd_v7_0_sriov_start()
957 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); in uvd_v7_0_start()
1598 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
Dvcn_v1_0.c474 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c564 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v2_5_disable_clock_gating()
Dvcn_v2_0.c500 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v2_0_disable_clock_gating()
Dvcn_v3_0.c661 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h441 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro
Duvd_4_0_sh_mask.h36 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L macro
Duvd_4_2_sh_mask.h221 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
Duvd_3_1_sh_mask.h221 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
Duvd_5_0_sh_mask.h241 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
Duvd_6_0_sh_mask.h243 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h934 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro
Dvcn_2_5_sh_mask.h2002 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro
Dvcn_2_0_0_sh_mask.h1953 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro
Dvcn_3_0_0_sh_mask.h2732 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK … macro