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Searched refs:UVD_CGC_CTRL__MPC_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h458 #define UVD_CGC_CTRL__MPC_MODE_MASK macro
Duvd_4_0_sh_mask.h48 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L macro
Duvd_4_2_sh_mask.h255 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
Duvd_3_1_sh_mask.h255 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
Duvd_5_0_sh_mask.h277 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
Duvd_6_0_sh_mask.h279 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c518 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v1_0_disable_clock_gating()
619 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v1_0_enable_clock_gating()
677 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c610 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_5_disable_clock_gating()
687 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
749 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_5_enable_clock_gating()
Dvcn_v2_0.c543 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_0_disable_clock_gating()
619 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
681 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v3_0.c707 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v3_0_disable_clock_gating()
806 UVD_CGC_CTRL__MPC_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
865 | UVD_CGC_CTRL__MPC_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v5_0.c676 UVD_CGC_CTRL__MPC_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1336 UVD_CGC_CTRL__MPC_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1616 UVD_CGC_CTRL__MPC_MODE_MASK |
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h951 #define UVD_CGC_CTRL__MPC_MODE_MASK macro
Dvcn_2_5_sh_mask.h2019 #define UVD_CGC_CTRL__MPC_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h1970 #define UVD_CGC_CTRL__MPC_MODE_MASK macro
Dvcn_3_0_0_sh_mask.h2749 #define UVD_CGC_CTRL__MPC_MODE_MASK macro