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Searched refs:UVD_CGC_CTRL__RBC_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h453 #define UVD_CGC_CTRL__RBC_MODE_MASK macro
Duvd_4_0_sh_mask.h54 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L macro
Duvd_4_2_sh_mask.h245 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 macro
Duvd_3_1_sh_mask.h245 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 macro
Duvd_5_0_sh_mask.h267 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 macro
Duvd_6_0_sh_mask.h269 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c513 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v1_0_disable_clock_gating()
614 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v1_0_enable_clock_gating()
672 UVD_CGC_CTRL__RBC_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c605 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v2_5_disable_clock_gating()
682 UVD_CGC_CTRL__RBC_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
744 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v2_5_enable_clock_gating()
Dvcn_v2_0.c538 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v2_0_disable_clock_gating()
614 UVD_CGC_CTRL__RBC_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
676 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v3_0.c702 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v3_0_disable_clock_gating()
801 UVD_CGC_CTRL__RBC_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
860 | UVD_CGC_CTRL__RBC_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v5_0.c671 UVD_CGC_CTRL__RBC_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1331 UVD_CGC_CTRL__RBC_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1611 UVD_CGC_CTRL__RBC_MODE_MASK |
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h946 #define UVD_CGC_CTRL__RBC_MODE_MASK macro
Dvcn_2_5_sh_mask.h2014 #define UVD_CGC_CTRL__RBC_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h1965 #define UVD_CGC_CTRL__RBC_MODE_MASK macro
Dvcn_3_0_0_sh_mask.h2744 #define UVD_CGC_CTRL__RBC_MODE_MASK macro