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Searched refs:UVD_CGC_CTRL__SCPU_MODE_MASK (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h463 #define UVD_CGC_CTRL__SCPU_MODE_MASK macro
Duvd_4_0_sh_mask.h58 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L macro
Duvd_4_2_sh_mask.h265 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 macro
Duvd_3_1_sh_mask.h265 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 macro
Duvd_5_0_sh_mask.h287 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 macro
Duvd_6_0_sh_mask.h289 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c523 | UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v1_0_disable_clock_gating()
624 | UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v1_0_enable_clock_gating()
682 UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_0.c548 | UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v2_0_disable_clock_gating()
624 UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v2_0_clock_gating_dpg_mode()
686 | UVD_CGC_CTRL__SCPU_MODE_MASK); in vcn_v2_0_enable_clock_gating()
Duvd_v5_0.c682 UVD_CGC_CTRL__SCPU_MODE_MASK); in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1342 UVD_CGC_CTRL__SCPU_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1623 UVD_CGC_CTRL__SCPU_MODE_MASK);
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h956 #define UVD_CGC_CTRL__SCPU_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h1975 #define UVD_CGC_CTRL__SCPU_MODE_MASK macro