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Searched refs:UVD_CGC_CTRL__SYS_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h449 #define UVD_CGC_CTRL__SYS_MODE_MASK macro
Duvd_4_0_sh_mask.h60 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L macro
Duvd_4_2_sh_mask.h237 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
Duvd_3_1_sh_mask.h237 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
Duvd_5_0_sh_mask.h259 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
Duvd_6_0_sh_mask.h261 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c509 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v1_0_disable_clock_gating()
610 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v1_0_enable_clock_gating()
668 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c601 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_5_disable_clock_gating()
678 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
740 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_5_enable_clock_gating()
Dvcn_v2_0.c534 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_0_disable_clock_gating()
610 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
672 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v3_0.c698 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v3_0_disable_clock_gating()
797 UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
856 | UVD_CGC_CTRL__SYS_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v5_0.c667 UVD_CGC_CTRL__SYS_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1327 UVD_CGC_CTRL__SYS_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1607 UVD_CGC_CTRL__SYS_MODE_MASK |
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h942 #define UVD_CGC_CTRL__SYS_MODE_MASK macro
Dvcn_2_5_sh_mask.h2010 #define UVD_CGC_CTRL__SYS_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h1961 #define UVD_CGC_CTRL__SYS_MODE_MASK macro
Dvcn_3_0_0_sh_mask.h2740 #define UVD_CGC_CTRL__SYS_MODE_MASK macro