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Searched refs:UVD_CGC_CTRL__VCPU_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h462 #define UVD_CGC_CTRL__VCPU_MODE_MASK macro
Duvd_4_0_sh_mask.h74 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L macro
Duvd_4_2_sh_mask.h263 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 macro
Duvd_3_1_sh_mask.h263 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 macro
Duvd_5_0_sh_mask.h285 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 macro
Duvd_6_0_sh_mask.h287 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c522 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v1_0_disable_clock_gating()
623 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v1_0_enable_clock_gating()
681 UVD_CGC_CTRL__VCPU_MODE_MASK | in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c614 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v2_5_disable_clock_gating()
691 UVD_CGC_CTRL__VCPU_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
753 | UVD_CGC_CTRL__VCPU_MODE_MASK); in vcn_v2_5_enable_clock_gating()
Dvcn_v2_0.c547 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v2_0_disable_clock_gating()
623 UVD_CGC_CTRL__VCPU_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
685 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v3_0.c711 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v3_0_disable_clock_gating()
810 UVD_CGC_CTRL__VCPU_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
869 | UVD_CGC_CTRL__VCPU_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v5_0.c680 UVD_CGC_CTRL__VCPU_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1340 UVD_CGC_CTRL__VCPU_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1620 UVD_CGC_CTRL__VCPU_MODE_MASK |
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h955 #define UVD_CGC_CTRL__VCPU_MODE_MASK macro
Dvcn_2_5_sh_mask.h2023 #define UVD_CGC_CTRL__VCPU_MODE_MASK macro
Dvcn_2_0_0_sh_mask.h1974 #define UVD_CGC_CTRL__VCPU_MODE_MASK macro
Dvcn_3_0_0_sh_mask.h2753 #define UVD_CGC_CTRL__VCPU_MODE_MASK macro