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Searched refs:UVD_CGC_GATE__LMI_MC_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c629 UVD_CGC_GATE__LMI_MC_MASK |
661 UVD_CGC_GATE__LMI_MC_MASK |
1277 UVD_CGC_GATE__LMI_MC_MASK | in uvd_v6_0_enable_clock_gating()
1366 UVD_CGC_GATE__LMI_MC_MASK |
Duvd_v5_0.c618 UVD_CGC_GATE__LMI_MC_MASK | in uvd_v5_0_enable_clock_gating()
705 UVD_CGC_GATE__LMI_MC_MASK |
Duvd_v7_0.c1648 UVD_CGC_GATE__LMI_MC_MASK |
Dvcn_v1_0.c486 | UVD_CGC_GATE__LMI_MC_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c575 | UVD_CGC_GATE__LMI_MC_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v2_0.c511 | UVD_CGC_GATE__LMI_MC_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v3_0.c672 | UVD_CGC_GATE__LMI_MC_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h402 #define UVD_CGC_GATE__LMI_MC_MASK macro
Duvd_4_0_sh_mask.h82 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L macro
Duvd_4_2_sh_mask.h133 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 macro
Duvd_3_1_sh_mask.h133 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 macro
Duvd_5_0_sh_mask.h145 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 macro
Duvd_6_0_sh_mask.h147 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h830 #define UVD_CGC_GATE__LMI_MC_MASK macro
Dvcn_2_5_sh_mask.h1900 #define UVD_CGC_GATE__LMI_MC_MASK macro
Dvcn_2_0_0_sh_mask.h1849 #define UVD_CGC_GATE__LMI_MC_MASK macro
Dvcn_3_0_0_sh_mask.h2630 #define UVD_CGC_GATE__LMI_MC_MASK macro