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Searched refs:UVD_CGC_GATE__UDEC_MP_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c639 UVD_CGC_GATE__UDEC_MP_MASK |
672 UVD_CGC_GATE__UDEC_MP_MASK |
1288 UVD_CGC_GATE__UDEC_MP_MASK | in uvd_v6_0_enable_clock_gating()
1376 UVD_CGC_GATE__UDEC_MP_MASK |
Duvd_v5_0.c628 UVD_CGC_GATE__UDEC_MP_MASK | in uvd_v5_0_enable_clock_gating()
715 UVD_CGC_GATE__UDEC_MP_MASK |
Duvd_v7_0.c1658 UVD_CGC_GATE__UDEC_MP_MASK |
Dvcn_v1_0.c497 | UVD_CGC_GATE__UDEC_MP_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c586 | UVD_CGC_GATE__UDEC_MP_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v2_0.c522 | UVD_CGC_GATE__UDEC_MP_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v3_0.c683 | UVD_CGC_GATE__UDEC_MP_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h413 #define UVD_CGC_GATE__UDEC_MP_MASK macro
Duvd_4_0_sh_mask.h109 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L macro
Duvd_4_2_sh_mask.h155 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 macro
Duvd_3_1_sh_mask.h155 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 macro
Duvd_5_0_sh_mask.h167 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 macro
Duvd_6_0_sh_mask.h169 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h841 #define UVD_CGC_GATE__UDEC_MP_MASK macro
Dvcn_2_5_sh_mask.h1911 #define UVD_CGC_GATE__UDEC_MP_MASK macro
Dvcn_2_0_0_sh_mask.h1860 #define UVD_CGC_GATE__UDEC_MP_MASK macro
Dvcn_3_0_0_sh_mask.h2641 #define UVD_CGC_GATE__UDEC_MP_MASK macro