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Searched refs:UVD_CGC_GATE__VCPU_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c641 UVD_CGC_GATE__VCPU_MASK |
674 UVD_CGC_GATE__VCPU_MASK |
1295 data3 |= UVD_CGC_GATE__VCPU_MASK; in uvd_v6_0_enable_clock_gating()
1378 UVD_CGC_GATE__VCPU_MASK |
Duvd_v5_0.c634 data3 |= UVD_CGC_GATE__VCPU_MASK; in uvd_v5_0_enable_clock_gating()
717 UVD_CGC_GATE__VCPU_MASK |
Duvd_v7_0.c1660 UVD_CGC_GATE__VCPU_MASK |
Dvcn_v1_0.c499 | UVD_CGC_GATE__VCPU_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c588 | UVD_CGC_GATE__VCPU_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v2_0.c524 | UVD_CGC_GATE__VCPU_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v3_0.c685 | UVD_CGC_GATE__VCPU_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h415 #define UVD_CGC_GATE__VCPU_MASK macro
Duvd_4_0_sh_mask.h114 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L macro
Duvd_4_2_sh_mask.h159 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
Duvd_3_1_sh_mask.h159 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
Duvd_5_0_sh_mask.h171 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
Duvd_6_0_sh_mask.h173 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h843 #define UVD_CGC_GATE__VCPU_MASK macro
Dvcn_2_5_sh_mask.h1913 #define UVD_CGC_GATE__VCPU_MASK macro
Dvcn_2_0_0_sh_mask.h1862 #define UVD_CGC_GATE__VCPU_MASK macro
Dvcn_3_0_0_sh_mask.h2643 #define UVD_CGC_GATE__VCPU_MASK macro