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Searched refs:UVD_CGC_STATUS__MPC_SCLK_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h166 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L macro
Duvd_4_2_sh_mask.h201 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 macro
Duvd_3_1_sh_mask.h201 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 macro
Duvd_5_0_sh_mask.h217 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 macro
Duvd_6_0_sh_mask.h219 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h897 #define UVD_CGC_STATUS__MPC_SCLK_MASK … macro
Dvcn_2_5_sh_mask.h1966 #define UVD_CGC_STATUS__MPC_SCLK_MASK … macro
Dvcn_2_0_0_sh_mask.h1916 #define UVD_CGC_STATUS__MPC_SCLK_MASK … macro
Dvcn_3_0_0_sh_mask.h2696 #define UVD_CGC_STATUS__MPC_SCLK_MASK … macro