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Searched refs:UVD_CGC_UDEC_STATUS__CM_VCLK_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h212 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L macro
Duvd_4_2_sh_mask.h277 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
Duvd_3_1_sh_mask.h277 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
Duvd_5_0_sh_mask.h301 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
Duvd_6_0_sh_mask.h303 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2046 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
Dvcn_2_0_0_sh_mask.h1998 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
Dvcn_3_0_0_sh_mask.h2776 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro