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Searched refs:UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h213 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005 macro
Duvd_4_2_sh_mask.h278 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
Duvd_3_1_sh_mask.h278 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
Duvd_5_0_sh_mask.h302 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
Duvd_6_0_sh_mask.h304 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2031 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT … macro
Dvcn_2_0_0_sh_mask.h1983 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2761 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT … macro