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Searched refs:UVD_GPCOM_VCPU_DATA0__DATA0_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h121 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK … macro
Duvd_4_0_sh_mask.h254 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL macro
Duvd_4_2_sh_mask.h47 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff macro
Duvd_3_1_sh_mask.h47 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff macro
Duvd_5_0_sh_mask.h47 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff macro
Duvd_6_0_sh_mask.h47 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h311 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK … macro
Dvcn_2_5_sh_mask.h2200 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK … macro
Dvcn_2_0_0_sh_mask.h3171 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK … macro
Dvcn_3_0_0_sh_mask.h2966 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK … macro