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Searched refs:UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h505 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT … macro
Duvd_4_0_sh_mask.h351 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h350 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
Duvd_3_1_sh_mask.h346 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h382 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h384 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1027 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT … macro
Dvcn_2_5_sh_mask.h3347 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2396 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT … macro
Dvcn_3_0_0_sh_mask.h4659 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v7_0.c868 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in uvd_v7_0_sriov_start()
983 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in uvd_v7_0_start()
Dvcn_v1_0.c994 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in vcn_v1_0_start_dpg_mode()
1049 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in vcn_v1_0_start_dpg_mode()
Duvd_v6_0.c744 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in uvd_v6_0_start()
Dvcn_v2_5.c810 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in vcn_v2_5_start_dpg_mode()
Dvcn_v2_0.c832 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in vcn_v2_0_start_dpg_mode()
Dvcn_v3_0.c934 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | in vcn_v3_0_start_dpg_mode()