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Searched refs:UVD_MPC_CNTL__PERF_RST_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h486 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L macro
Duvd_4_2_sh_mask.h473 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 macro
Duvd_3_1_sh_mask.h469 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 macro
Duvd_5_0_sh_mask.h505 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 macro
Duvd_6_0_sh_mask.h507 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2837 #define UVD_MPC_CNTL__PERF_RST_MASK … macro
Dvcn_2_0_0_sh_mask.h2602 #define UVD_MPC_CNTL__PERF_RST_MASK … macro
Dvcn_3_0_0_sh_mask.h3910 #define UVD_MPC_CNTL__PERF_RST_MASK … macro