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Searched refs:UVD_MPC_CNTL__PERF_RST__SHIFT (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h487 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006 macro
Duvd_4_2_sh_mask.h474 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 macro
Duvd_3_1_sh_mask.h470 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 macro
Duvd_5_0_sh_mask.h506 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 macro
Duvd_6_0_sh_mask.h508 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2831 #define UVD_MPC_CNTL__PERF_RST__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2596 #define UVD_MPC_CNTL__PERF_RST__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3902 #define UVD_MPC_CNTL__PERF_RST__SHIFT … macro