Home
last modified time | relevance | path

Searched refs:UVD_MPC_SET_MUXA0__VARA_0_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h603 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
Duvd_4_0_sh_mask.h496 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL macro
Duvd_4_2_sh_mask.h481 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
Duvd_3_1_sh_mask.h477 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
Duvd_5_0_sh_mask.h513 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
Duvd_6_0_sh_mask.h515 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1110 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
Dvcn_2_5_sh_mask.h2851 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
Dvcn_2_0_0_sh_mask.h2616 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
Dvcn_3_0_0_sh_mask.h3924 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro