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Searched refs:UVD_MPC_SET_MUXA0__VARA_1__SHIFT (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h599 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
Duvd_4_0_sh_mask.h499 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 macro
Duvd_4_2_sh_mask.h484 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
Duvd_3_1_sh_mask.h480 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
Duvd_5_0_sh_mask.h516 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
Duvd_6_0_sh_mask.h518 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1106 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
Dvcn_2_5_sh_mask.h2847 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2612 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3920 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c830 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_spg_mode()
1013 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c821 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
975 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start()
Dvcn_v2_0.c843 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start_dpg_mode()
978 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start()
Dvcn_v3_0.c945 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start_dpg_mode()
1102 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start()