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Searched refs:UVD_MPC_SET_MUXA0__VARA_4__SHIFT (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h602 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
Duvd_4_0_sh_mask.h505 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 macro
Duvd_4_2_sh_mask.h490 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
Duvd_3_1_sh_mask.h486 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
Duvd_5_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
Duvd_6_0_sh_mask.h524 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1109 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
Dvcn_2_5_sh_mask.h2850 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2615 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3923 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c833 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v1_0_start_spg_mode()
1016 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c824 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
978 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v2_5_start()
Dvcn_v2_0.c846 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
981 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v2_0_start()
Dvcn_v3_0.c948 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1105 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v3_0_start()