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Searched refs:UVD_MPC_SET_MUXB0__VARB_2__SHIFT (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h618 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
Duvd_4_0_sh_mask.h517 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c macro
Duvd_4_2_sh_mask.h502 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
Duvd_3_1_sh_mask.h498 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
Duvd_5_0_sh_mask.h534 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
Duvd_6_0_sh_mask.h536 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1125 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
Dvcn_2_5_sh_mask.h2866 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2631 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3939 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c837 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v1_0_start_spg_mode()
1020 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c829 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_start_dpg_mode()
983 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_start()
Dvcn_v2_0.c851 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_0_start_dpg_mode()
986 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_0_start()
Dvcn_v3_0.c953 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v3_0_start_dpg_mode()
1110 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v3_0_start()