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Searched refs:UVD_MPC_SET_MUXB1__VARB_7_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h632 #define UVD_MPC_SET_MUXB1__VARB_7_MASK … macro
Duvd_4_0_sh_mask.h526 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L macro
Duvd_4_2_sh_mask.h511 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 macro
Duvd_3_1_sh_mask.h507 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 macro
Duvd_5_0_sh_mask.h543 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 macro
Duvd_6_0_sh_mask.h545 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1139 #define UVD_MPC_SET_MUXB1__VARB_7_MASK … macro
Dvcn_2_5_sh_mask.h2880 #define UVD_MPC_SET_MUXB1__VARB_7_MASK … macro
Dvcn_2_0_0_sh_mask.h2645 #define UVD_MPC_SET_MUXB1__VARB_7_MASK … macro
Dvcn_3_0_0_sh_mask.h3953 #define UVD_MPC_SET_MUXB1__VARB_7_MASK … macro