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Searched refs:UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h743 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK … macro
Duvd_4_0_sh_mask.h598 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L macro
Duvd_4_2_sh_mask.h619 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 macro
Duvd_3_1_sh_mask.h613 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 macro
Duvd_5_0_sh_mask.h681 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 macro
Duvd_6_0_sh_mask.h683 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1270 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK … macro
Dvcn_2_5_sh_mask.h2917 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK … macro
Dvcn_2_0_0_sh_mask.h2888 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK … macro
Dvcn_3_0_0_sh_mask.h3997 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c419 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
Dvcn_v1_0.c941 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in vcn_v1_0_start_spg_mode()
1099 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in vcn_v1_0_start_dpg_mode()
Duvd_v7_0.c1090 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v7_0_start()