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Searched refs:UVD_SUVD_CGC_GATE__SDB_HEVC_MASK (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c655 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
688 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
1270 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; in uvd_v6_0_enable_clock_gating()
Dvcn_v1_0.c540 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c632 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v2_0.c565 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v3_0.c728 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h238 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
Duvd_5_0_sh_mask.h747 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
Duvd_6_0_sh_mask.h749 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h466 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
Dvcn_2_5_sh_mask.h2095 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
Dvcn_2_0_0_sh_mask.h3221 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
Dvcn_3_0_0_sh_mask.h2831 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro