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Searched refs:UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h193 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK … macro
Duvd_4_0_sh_mask.h738 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L macro
Duvd_4_2_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
Duvd_3_1_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
Duvd_5_0_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
Duvd_6_0_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h415 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK … macro