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Searched refs:UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h646 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
Duvd_4_0_sh_mask.h749 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h524 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
Duvd_3_1_sh_mask.h520 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h556 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h558 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1166 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
Dvcn_2_5_sh_mask.h2676 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2672 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3734 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro