Searched refs:UVD_VCPU_CNTL__CLK_EN_MASK (Results 1 – 16 of 16) sorted by relevance
794 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()855 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()952 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_5_start()1381 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_5_stop()
918 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()979 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()1071 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v3_0_start()1510 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v3_0_stop()
816 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_0_start_dpg_mode()956 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_0_start()1170 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_0_stop()
853 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()984 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v1_0_start_dpg_mode()1147 ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_stop_spg_mode()
881 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_sriov_start()1012 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_start()
771 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
665 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
768 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
1187 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
3818 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro