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Searched refs:UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h783 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014 macro
Duvd_4_2_sh_mask.h562 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
Duvd_3_1_sh_mask.h558 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
Duvd_5_0_sh_mask.h596 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
Duvd_6_0_sh_mask.h598 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1186 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
Dvcn_2_5_sh_mask.h2752 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2750 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3810 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_5.c793 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
854 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
Dvcn_v3_0.c917 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v3_0_start_dpg_mode()
978 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v3_0_start_dpg_mode()
Dvcn_v1_0.c983 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c815 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_0_start_dpg_mode()