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Searched refs:UVD_VCPU_CNTL__TRCE_MUX__SHIFT (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h791 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b macro
Duvd_4_2_sh_mask.h552 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
Duvd_3_1_sh_mask.h548 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
Duvd_5_0_sh_mask.h584 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
Duvd_6_0_sh_mask.h586 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2749 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2745 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3807 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro