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Searched refs:VCLK (Results 1 – 12 of 12) sorted by relevance

/drivers/video/fbdev/sis/
Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2272 unsigned int longtemp = VCLK * colordepth; in SiS_DoCalcDelay()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
2316 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
2407 unsigned short i, data, VCLK, MCLK16, colorth = 0; in SiS_SetCRT1FIFO_630() local
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Dinit301.c5337 unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0; in SiS_SetCRT2FIFO_300() local
5357 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5369 VCLK = SiS_Pr->CSRClock_CRT1; in SiS_SetCRT2FIFO_300()
5390 data2 = temp - ((colorth * VCLK) / MCLK); in SiS_SetCRT2FIFO_300()
5447 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5452 VCLK = ROMAddr[0x229] | (ROMAddr[0x22a] << 8); in SiS_SetCRT2FIFO_300()
5461 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT2FIFO_300()
5469 data = data * VCLK * colorth; in SiS_SetCRT2FIFO_300()
/drivers/usb/misc/sisusbvga/
Dsisusb_init.c633 unsigned short data = 0, VCLK = 0, index = 0; in SiS_SetVCLKState() local
637 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
640 if (VCLK >= 166) in SiS_SetVCLKState()
644 if (VCLK >= 166) in SiS_SetVCLKState()
649 if (VCLK >= 260) in SiS_SetVCLKState()
651 else if (VCLK >= 160) in SiS_SetVCLKState()
653 else if (VCLK >= 135) in SiS_SetVCLKState()
/drivers/gpu/drm/amd/pm/inc/
Dpower_state.h143 uint32_t VCLK; member
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dprocesspptables.c762 ps->uvd_clocks.VCLK = le32_to_cpu(pnon_clock_info->ulVCLK); in init_non_clock_fields()
765 ps->uvd_clocks.VCLK = 0; in init_non_clock_fields()
Dsmu10_hwmgr.c849 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu10_dpm_get_pp_table_entry()
Dsmu7_hwmgr.c3261 power_state->uvd_clocks.VCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3354 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v1()
3502 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v0()
Dsmu8_hwmgr.c1415 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
Dvega10_hwmgr.c3140 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3218 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in vega10_get_pp_table_entry()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c156 CLK_MAP(VCLK, PPCLK_VCLK),
Darcturus_ppt.c155 CLK_MAP(VCLK, PPCLK_VCLK),
Dsienna_cichlid_ppt.c141 CLK_MAP(VCLK, PPCLK_VCLK_0),