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Searched refs:VISLANDS30_IV_SRCID_D6_V_UPDATE_INT (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/ivsrcid/
Divsrcid_vislands30.h60 #define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11 macro
/drivers/gpu/drm/amd/display/dc/irq/dce60/
Dirq_service_dce60.c316 case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT: in to_dal_irq_source_dce60()
/drivers/gpu/drm/amd/display/dc/irq/dce110/
Dirq_service_dce110.c350 case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT: in to_dal_irq_source_dce110()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c2769 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { in dce110_register_irq_handlers()