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Searched refs:VM_CONTEXT1_CNTL (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c224 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_setup_vmid_config()
225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_setup_vmid_config()
227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
238 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
242 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
[all …]
Dmmhub_v1_0.c248 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_setup_vmid_config()
249 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_0_setup_vmid_config()
251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
253 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
258 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
260 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
262 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
266 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
[all …]
Dgmc_v8_0.c756 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
758 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
760 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
762 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
764 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
766 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
768 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
939 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
940 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
[all …]
Dgmc_v7_0.c525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
531 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
533 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
535 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v7_0_gart_enable()
692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v7_0_gart_enable()
Dgmc_v6_0.c398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
400 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
402 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
404 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
406 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
408 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v6_0_set_fault_enable_default()
Dsid.h409 #define VM_CONTEXT1_CNTL 0x505 macro
/drivers/gpu/drm/radeon/
Dnid.h143 #define VM_CONTEXT1_CNTL 0x1414 macro
Dni.c1335 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
1369 WREG32(VM_CONTEXT1_CNTL, 0); in cayman_pcie_gart_disable()
Dsid.h408 #define VM_CONTEXT1_CNTL 0x1414 macro
Dcikd.h526 #define VM_CONTEXT1_CNTL 0x1414 macro
Devergreen.c2445 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2461 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2511 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
Devergreend.h1140 #define VM_CONTEXT1_CNTL 0x1414 macro
Dsi.c4354 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4392 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
Dcik.c5490 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5561 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()