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Searched refs:WB_EC_CONFIG (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dwb.h59 SRI2(WB_EC_CONFIG, CNV, inst),\
107 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
108 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
115 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.c74 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1, in dwb1_enable()
98 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0, in dwb1_disable()
Ddcn10_dwb.h55 SRI(WB_EC_CONFIG, CNV, inst),\
218 uint32_t WB_EC_CONFIG; member