Home
last modified time | relevance | path

Searched refs:WREG32_AND (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Dr600_hdmi.c374 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, in r600_set_audio_packet()
401 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); in r600_set_mute()
456 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings()
490 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable()
498 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable()
506 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); in r600_hdmi_enable()
Devergreen_hdmi.c397 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); in dce4_set_mute()
425 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
429 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
484 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
Ddce3_1_afmt.c231 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); in dce3_2_set_mute()
Devergreen.c1748 WREG32_AND(DC_HPDx_INT_CONTROL(hpd), ~DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity()
4487 WREG32_AND(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_POLARITY); in evergreen_disable_interrupt_state()
Dradeon.h2555 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) macro
Dsi.c5977 WREG32_AND(DC_HPDx_INT_CONTROL(i), in si_disable_interrupt_state()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu.h1099 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) macro
/drivers/misc/habanalabs/common/
Dhabanalabs.h1312 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) macro
/drivers/misc/habanalabs/goya/
Dgoya.c645 WREG32_AND(reg, ~0x7FF); in goya_mmu_prepare_reg()
1304 WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, in _goya_tpc_mbist_workaround()
2480 WREG32_AND(mmSTLB_STLB_FEATURE_EN, in goya_mmu_init()
/drivers/misc/habanalabs/gaudi/
Dgaudi.c4756 WREG32_AND(reg, ~0x7FF); in gaudi_mmu_prepare_reg()
4991 WREG32_AND(mmDMA0_CORE_PROT + dma_offset, in gaudi_send_job_on_qman0()